Turbo codes

  • ccgen - an automatic tool for VHDL convolutional coder generation:

  • Turbo NOC: Network On Chip based turbo decoder architectures:

  • Related publications:
    • M.Martina and G. Masera, "Flexible blocks for high throughput Serially Concatenated Convolutional Codes", ACM Great Lakes Symposium on VLSI, Mar. 2007
    • M. Martina and G. Masera, "Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures", IEEE Transactions on Circuits and Systems I, vol. 57, n. 10, pp. 2776-2789, Oct. 2010
    • M. Martina, G. Masera, H. Moussa and A. Baghdadi, "On chip interconnects for multiprocessor turbo decoding architectures", Elsevier Microprocessors and Microsystems, vol. 35, n. 1, pp. 167-181, Mar. 2011
    • M. Martina and G. Masera, "Improving Network-on-Chip-based turbo decoder architectures", Springer Journal of Signal Processing Systems, vol. 73, n. 1, pp. 83-100, Jan 2013
    • C. Condo, M. Martina and G. Masera, "A Network-on-Chip-based turbo/LDPC decoder architecture", Design, Automation and Test in Europe Conference and Exhibition, Mar. 2012
    • C. Condo, M. Martina and G. Masera, "VLSI implementation of a multi-mode turbo/LDPC decoder architecture", IEEE Transactions on Circuits and Systems I, vol. 60, n. 6, pp. 1441-1454, Jun. 2013
    • C. Condo, M. Martina, M. Ruo Roch and G. Masera, "Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications", Euromicro International Conference on Parallel, Distributed and network-based Processing - Special Session: On-Chip Parallel and Network-Based Systems, Feb. 2014

+39 011 090 4205 +39 011 090 4217 maurizio.martina@polito.it